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PLANE-BASED REGISTRATION OF SEVERAL THOUSAND LASER SCANS ON STANDARD HARDWARE
Terrestrial laser scanning registration plane-to-plane correspondences stochastic modelling large networks
2018/6/5
The automatic registration of terrestrial laser scans appears to be a solved problem in science as well as in practice. However, this assumption is questionable especially in the context of large proj...
Hardware Requirements for Optical Circuit Switched Data Center Networks
Optical interconnects Switching Networks circuit-switched
2015/5/22
Based on measurements of a prototype, we identify hardware requirements for improving the performance of hybrid electrical-packet-switched/optical-circuit-switched data center networks.
Optical Network Design Algorithms that Consider Optical Path Add/Drop Ratio Restrictions for OXC Hardware Scale Reduction
Optical Network Design Algorithms Hardware Scale Add/Drop Ratio
2015/5/18
We develop network design algorithms that consider constraints on the number of added/dropped optical paths at nodes in terms of wavelength and of fiber. The strategy is demonstrated to significantly ...
This paper presents a hardware accelerated QoT estimation tool used in the DICONET impairment-aware optical network. Performance evaluation is given by examining different network scenarios in terms o...
Optimal Hardware Module Planning and Switch Backplane Configuration for Layer-One Traffic Grooming
Networks network optimization
2015/6/5
We present an automatic hardware module planning approach for optical transport networks. An optimal switch backplane size is identified that can achieve the most cost-effective hardware module planni...
Custom Hardware Processor to Compute a Figure of Merit for the Fit of X-Ray Diffraction Peaks
Custom Hardware Processor Compute a Figure of Merit for the Fit of X-Ray Diffraction Peaks
2009/9/4
A custom processor based on reconfigurable hardware technology is proposed in order to compute the figure of merit used to measure the quality of the fit of X-ray diffraction peaks. As the experimenta...
Hardware Based Scalable Path Computation Engine for Multilayer Traffic Engineering in GMPLS networks
Hardware Scalable Path Computation Engine Multilayer Traffic Engineering GMPLS networks
2015/8/4
A parallel data-flow hardware based path computation engine that makes multilayer traffic engineering more scalable is proposed. The engine achieves 100 times faster than conventional path computation...